[MLton-commit] r7501

[Matthew Fluet]

 Fixed bug in amd64 codegen calling convention for varargs C calls.


----------------------------------------------------------------------

U   mlton/trunk/doc/changelog
U   mlton/trunk/mlton/codegen/amd64-codegen/amd64-generate-transfers.fun

----------------------------------------------------------------------

Modified: mlton/trunk/doc/changelog
===================================================================
--- mlton/trunk/doc/changelog	2011-01-17 20:56:39 UTC (rev 7500)
+++ mlton/trunk/doc/changelog	2011-02-06 01:46:28 UTC (rev 7501)
@@ -1,3 +1,13 @@
+Here are the changes from version 2010608 to version YYYYMMDD.
+
+* 2011-02-05
+   - Fixed bug in amd64 codegen calling convention for varargs C calls.
+
+* 2011-01-17
+   - Fixed bug in comment-handling in lexer for mlyacc's input language.
+
+--------------------------------------------------------------------------------
+
 Here are the changes from version 20070826 to version 20100608.
 
 Summary:

Modified: mlton/trunk/mlton/codegen/amd64-codegen/amd64-generate-transfers.fun
===================================================================
--- mlton/trunk/mlton/codegen/amd64-codegen/amd64-generate-transfers.fun	2011-01-17 20:56:39 UTC (rev 7500)
+++ mlton/trunk/mlton/codegen/amd64-codegen/amd64-generate-transfers.fun	2011-02-06 01:46:28 UTC (rev 7501)
@@ -1357,6 +1357,31 @@
                                     size = pointerSize})),
                                  size_stack_args + 32)
                            else (setup_args, size_stack_args)
+                     (* SysV ABI AMD64 requires %rax set to the number
+                      * of xmms registers passed for varags functions;
+                      * since %rax is caller-save, we conservatively 
+                      * set %rax for all functions (not just varargs).
+                      *)
+                     val (reg_args, setup_args) =
+                        if not win64
+                           then let
+                                   val mem = applyFFTempRegArg 8
+                                   val reg = Register.rax
+                                in
+                                   ((mem,reg) :: reg_args,
+                                    AppendList.append
+                                    (setup_args,
+                                     AppendList.fromList
+                                     [Assembly.instruction_mov
+                                      {src = Operand.immediate_int (List.length xmmreg_args),
+                                       dst = Operand.memloc mem,
+                                       size = Size.QUAD},
+                                      Assembly.directive_cache
+                                      {caches = [{register = reg,
+                                                  memloc = mem,
+                                                  reserve = true}]}]))
+                                end
+                        else (reg_args, setup_args)
                      (*
                      val reserve_args =
                         AppendList.fromList