x86 backend design (fwd)

[Matthew Fluet]

---------- Forwarded message ----------
Date: Tue, 20 Jun 2000 20:27:38 -0500
From: Henry Cejtin <henry@clairv.com>
To: fluet@research.nj.nec.com
Subject: Re: x86 backend design

Segment registers?  I'm really confused now.  At least under linux, every
thing looks like a flat 32 bit address space.  I.e., ss, ds and es are all
the same.  This is pretty much required since other wise you would have to
do funny things for certain weird instructions that use certain segments
(like the stack ones that use the ss and the string instructions that use
the es). Were you thinking of trying to use the segment registers for
something else? I don't even know if that is allowed, but I would think
that it would certainly be a mistake.  (Note, reloading segment registers
is quite expensive.)

As to x86 idiosyncracies (and it is pretty idiosyncratic) my impression
was that on P6's and better (i.e., all we care about) it didn't buy you
much to use any of the strange instructions or pay too much attention.  
One exception to this is that you REALLY don't want to use both small
parts of a big register and the whole register.  I.e., the code sequence
which clears eax and then loads a byte into al and then uses eax is VERY
VERY bad.  This is because the register renaming in the chip suffers big
time.  As I recall, the whole out-of-order pipeline grinds to a halt.


---------- Forwarded message ----------
Date: Wed, 21 Jun 2000 10:24:16 -0400 (EDT)
From: Matthew Fluet <fluet@research.nj.nec.com>
To: Henry Cejtin <henry@clairv.com>
Subject: Re: x86 backend design


> Segment  registers?   I'm  really  confused now.  At least under linux, every
> thing looks like a flat 32 bit address space.  I.e., ss, ds and  es  are  all
> the same.  This is pretty much required since other wise you would have to do
> funny things for certain weird instructions that use certain  segments  (like
> the  stack ones that use the ss and the string instructions that use the es).

You're absolutely right.  I'm still coming up to speed with x86 and some
of the linux specifics, so I wasn't sure if the segment registers were set
like they are in some other systems.

> As  to  x86 idiosyncracies (and it is pretty idiosyncratic) my impression was
> that on P6's and better (i.e., all we care about) it didn't buy you  much  to
> use any of the strange instructions or pay too much attention.  One exception
> to this is that you REALLY don't want to  use  both  small  parts  of  a  big
> register  and  the  whole register.  I.e., the code sequence which clears eax
> and then loads a byte into al and then uses eax is VERY VERY  bad.   This  is
> because the register renaming in the chip suffers big time.  As I recall, the
> whole out-of-order pipeline grinds to a halt.

So, instead of 

movl $0,%eax
movb src,%al
addl $const,%eax

something like

movzbl src,%eax
addl $const,%eax

Is there any performance cost to using the small parts of the registers
themselves?  ML typing should really limit the cases of mixed size
operations to casts and maybe a couple of other places.  But, in a
sequence of word8 or char operations, is it better to upgrade them to 32
bits for the ops and then save only the low bits at the end?  (A quick
look at one of the Intel Optimization Manuals leads me to believe that it
might be benefitial to do so.)