x86-codegen bug

[Stephen Weeks]

I just checked in a bunch of changes to the ssa-branch.  What is currently there
passes all the regressions, but is not able to self compile due to an
x86-codegen bug.  Here's a snippet.

      x86 code gen starting
handling respill in toRegisterMemLoc
entries:
%edi MEM<l>{Stack}[(MEM<l>{GCStateHold}[((gcState+40))+(((0*4))*4)])+(((152*1))*1)] 1019 true NO
...
	jmp statementLimitCheckLoop_2022

# directive: Unreserve: registers: %esp %ebp 

make[1]: Leaving directory `/home/sweeks/mlton/src/mlton'
      x86 code gen raised in 32.01 + 22.59 (41% GC)
   Compile SML raised in 141.14 + 173.74 (55% GC)
MLton raised in 141.23 + 173.74 (55% GC)
mlton: x86AllocateRegister.allocateRegisters::toRegisterMemLoc:reSpill
Command exited with non-zero status 1
312.89user 2.18system 5:17.77elapsed 99%CPU (0avgtext+0avgdata 0maxresident)k
0inputs+0outputs (3168major+285013minor)pagefaults 0swaps
make[1]: *** [mlton-compile] Error 1

Matthew, if you could take a look, that would be great.  Once we get this bug
fixed and are able to self compile, I'd like to merge the ssa-branch into the
main line and continue replacing CPS with SSA.