[MLton-devel] benchmarks -align {4,8}
Stephen Weeks
MLton@mlton.org
Fri, 25 Apr 2003 15:00:37 -0700
> I'm really rather surprised at the slowdowns caused by aligning mod 8. The
> only way that this can happen that I know of is from wasting some space in
> the cache and also not getting stuff in cache line loads. I.e., if you have
> 2 ints which are adjacent then you have a good chance of getting them both
> with one cache line load if things are only aligned mod 4.
The slowdown makes sense to me. Objects can be 4 bytes larger in
order to make their size = 0 mod 8. This means that we burn through
more space when allocating and more is live when GCing. The benchmark
that is hurt worst on is DLXSimulator, which is essentially a list
reversal benchmark -- and lists are where we get hurt worst, with each
cons cell going from 12 to 16 bytes.
> Did you also align the stack?
Yes. The stack bottom, stack frames, and double slots are all
aligned (if they weren't we would see bus errors on SPARCs).
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