pseudo-register addressing

[Henry Cejtin]

I don't follow.  The part of the stack (the cache line) with the return address
is in the cache, but the rest isn't.
To be concrete: if I have code which makes, say, 100 non-tail calls (so 100
frames get pushed on the stack) and then they all return, and each frame ends
up using 1K space, then the frames won't all fit in the L1 cache.  Thus if
I have pseudo-registers in each frame, then for each entry, the first time I
write to a pseudo-register it misses the cache (and loads it).  On the other
hand, if I kept all my pseudo-registers in some other block of memory, then
all the routines would share them, and they would always be in level 1 cache.
The notion is that concentrating memory references into a smaller chunk of
memory is good because of the cache.