[MLton-devel] preload instructions

[Matthew Fluet]

> I was reading through the changelog for gcc 3.1 and read that they added code
> to generate pre-load instructions for the Intel architecture.  I.e., to start
> a  load going ahead of when they actually need the value.  This isn't easy to
> do using the x86 instruction set because of the lack  of  registers  you  can
> name to tie up with the result of the load.
> 
> I  mention  this because I would think that they wouldn't do this unless they
> saw a pretty big gain.

If you see any details on it, point it out.  I suspect there is a little
bit of low hanging fruit in the x86 codegen just in doing some
post reg. alloc. peephole and load hoisting.  We might also not be too bad
because most of the loads are from the pseudo-register array or the stack
-- both of which are accessed so often that they probably end up in the
caches.  And, heap accesses are always indirect, so I don't know how much
hoisting and pre-loading you could get.



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