[MLton] power pc "port"

[Stephen Weeks]

> Thanks for the details.  I'm inclined to agree with your reading of
> the standard.  Which would seem to indicate that gcc's behavior on
> x86 is in the wrong.

Can someone send C code for what they think is going wrong?

> I can understand why gcc "optimizes" things on the x86 where there
> are 8-bit registers and operations available.  I'm really curious to
> understand why (or whether) it is doing the right thing on Sparc. On
> that architecture, we should be in the same boat as with PowerPC --
> i.e., only 32-bit registers and operations.

Here's the assembly I get for Word8_neg when compiled with gcc -O1 on
various platforms.

----------------------------------------
G5
----------------------------------------
_Word8_neg:
	neg r3,r3
	rlwinm r3,r3,0,0xff
	blr

----------------------------------------
Sparc
----------------------------------------
Word8_neg:
	!#PROLOGUE# 0
	!#PROLOGUE# 1
	sub	%g0, %o0, %o0
	retl
	and	%o0, 0xff, %o0

----------------------------------------
x86
----------------------------------------
Word8_neg:
	pushl	%ebp
	movl	%esp, %ebp
	movb	8(%ebp), %al
	negl	%eax
	movzbl	%al, %eax
	leave
	ret